Rapid thermal processing (RTP) is a well developed technology for fabricating semiconductor integrated circuits in which the substrate, for example, a silicon wafer, is irradiated with high-intensity optical radiation to quickly heat the substrate to a relatively high temperature to thermally activate a process in the substrate. Once the substrate has been thermally processed, the radiant energy is removed and the substrate quickly cools. Thereby, the thermal budget is reduced because the RTP chamber itself is not heated to the elevated temperatures required for processing the substrate. RTP has been applied to a number of different applications including annealing, silicidation, oxidation and nitridation, etching, smoothing, and chemical vapor deposition as examples.
Conventionally RTP chambers have relied upon a large number of high-intensity lamps, for example, tungsten halogen lamps arranged in an array over a silicon wafer. The lamps can be quickly turned on and off, thereby achieving high thermal ramp-up and ramp-down rates on the wafer. However, advanced integrated circuits are demanding even quicker heating rates. Several laser-based RTP systems have been proposed in which a laser producing a relatively small beam is scanned over the surface of the wafer. In one type of scanned laser RTP system, 20 ns of pulsed laser radiation is directed to different small areas of the wafer. The high-intensity pulsed radiation very quickly heats the surface of the localized area to a high temperature without significantly heating the supporting substrate.
Another approach generates a narrow line beam of CW laser radiation which is scanned across the wafer in a direction transverse to the line. Thereby, the laser radiation strikes a particular area only for a relatively short time. Scanning of a linear CW beam thus also produces very high thermal heating rates of the surface without significantly heating the supporting substrate. The linear beam also inherently provides better uniformity than the pulsed spot beams characteristic of high-energy pulsed lasers. Jennings et al. describes such a scanned line beam in U.S. Published Application 2003/0196996, incorporated herein by reference in its entirety. Markle et al. disclose another type of such apparatus in U.S. Pat. No. 6,531,681.
Uniformity becomes a continuingly more stringent requirement for advanced integrated circuits. Non-uniformities may arise from present processing conditions or from prior stages of fabrication. Most processing, including RTP, assumes that the wafer being processed is substantially uniform on a macroscopic basis and the control system attempts to make the current process as uniform as possible. In any case, any improvement in uniformity simplifies the design of the integrated circuit and increases the fabrication yield.
Some types of processing afford control over radial profiles. For example, in rapid thermal processing (RTP), an array of high-intensity lamps is directed at a spinning wafer. The wafer rotation substantially guarantees circumferential uniformity of thermal processing. Several pyrometers or other temperature measuring devices are directed at different radii of the wafer and the lamp array is divided into multiple radial heating zones which are separately controlled. In typical operation, the amount of power delivered to the different heating zones is varied to provide a uniform temperature profile. In some situations, the heating control may be used to provide a radially non-uniform temperature profile. For example, in feed back control, one or more test wafers are thermally processed according to a set recipe and then characterized for any radial non-uniformity. The recipe for processing of future wafers is then modified with an adjusted radial heating pattern which reduces the observed radial non-uniformity. Similar feed back radial control has been practiced in chemical mechanical polishing (CMP) in which wafer rotation provides circumferential uniformity and a the radial pressure profile is adjusted to correct non-uniformities observed on test wafers.
Such feed back control suffers several disadvantages. First, it is substantially incapable of correcting a two-dimensional variation in uniformity, particularly when the non-uniformity arises in a previous step in which the wafer is not rotated to provide circumferential uniformity. Secondly, it assumes that any non-uniformities are not varying in time or from wafer to wafer.
Although the invention is not so limited, one technology area suffering from macroscopic non-uniformities involves silicon-on-insulator (SOI) wafers. SOI wafers are already applied to MEMS (micro electromechanical system) chips and are anticipated to be used in very advanced silicon integrated circuits. An SOI wafer 10, illustrated in cross section in FIG. 1, includes a silicon wafer 12 over which is deposited a dielectric layer 14, for examples, a silicon dioxide layer 14 deposited by CVD (chemical vapor deposition). A silicon layer 16 is then deposited over the dielectric layer 14 in another CVD process. The silicon layer 16 as deposited is typically polycrystalline. If desired, the polycrystalline silicon may be converted to monocrystalline silicon by techniques well known in SOI technology. The illustrated structure is usually formed in a blanket, unpatterned structure over an entire wafer.
In an alternative SOI technology, usually referred to as the Soitec process, heavy ions are implanted at a predetermined depth into a silicon donor wafer, which is then bonded to a silicon acceptor wafer with an oxide layer therebetween. The underlying donor wafer is then cleaved along the implantation line to leave a thin silicon surface layer overlying the oxide layer.
Standard semiconductor fabrication techniques, including CVD, sputtering, etching, and photolithography, are then used to form semiconductor or MEMS devices in and over the silicon layer 16. After the device definition, the SOI wafer 10 is diced into a number of integrated circuit chips. The SOI structure is particularly advantageous for semiconductor devices because the dielectric layer 14 insulates the devices from the silicon substrate 12 and thereby virtually eliminates leakage and parasitic capacitance between the devices and the substrate. However, device performance is enhanced if the silicon layer 16 is uniformly thick. Unfortunately, it often occurs that the as deposited silicon layer 16 has significant variations in thickness over lateral distances of many millimeters with an irregular pattern of peaks 17 and valleys 18 and these variations may vary in a two-dimensional pattern with no easily defined symmetry. Even a four-fold asymmetry is difficult to compensate. Although better process control may improve the thickness uniformity, it is desired to improve the thickness uniformity on already fabricated SOI wafers.
Accordingly, it is desired to provide a control system that affords greater and closer control especially in a thermal processing system.